Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)

This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area, power and speed. The paper analyzes the dynamic power consumption of the IP cores in the fabric of Field Programmable Gate Arrays (FPGAs). The target device is Virtex family (xcv1000). The cores are technology independent and runtime programmable. The results show an overall 61% power saving at an expense of 36% area (Slices used). The results demonstrate that the power saving is achieved by reducing switching activity in the cores. This reduction in switching activity is achieved by applying low power design techniques in to the MAC (multiply and accumulate) unit which is a power hungry component in FIR filters. The results are based on the comparison of 73 taps programmable cores with two 16X128 RAMs for data and coefficients.